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ICs for Communications
PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2
Data Sheet 02.97
T2306-0V22-D1-7600
30%530%7 5HYLVLRQ +LVWRU\ Previous Version: 01.94 Page Page (in previous (in new Version) Version) 14-15 19-20
&XUUHQW 9HUVLRQ Subjects (major changes since last revision)
$&'& &KDUDFWHULVWLFV H-input current ,H: is changed from 10A to 30A and L-input current ,L: is changed from -10A to -30A &ORFN IUHTXHQF\ ICL max. is changed from 10MHz to 12MHz; +SXOVHZLGWK &/ WWHCL min. is changed from 60ns to 40ns; +SXOVHZLGWK HQDEOH WWHENmin. is changed from 60ns to 40ns; Input reference frequency ICRI is changed from 20MHz to 22MHz ,QSXW 6LJQDO 5, Input voltage 9I: is changed from 20MHz to 22MHz
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26
18 19
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(GLWLRQ This edition was realized using the software system FrameMaker(R). 3XEOLVKHG E\ 6LHPHQV $* +/ ,7 6LHPHQV $* $OO 5LJKWV 5HVHUYHG $WWHQWLRQ SOHDVH As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. 3DFNLQJ Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. &RPSRQHQWV XVHG LQ OLIHVXSSRUW GHYLFHV RU V\VWHPV PXVW EH H[SUHVVO\ DXWKRUL]HG IRU VXFK SXUSRVH Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.
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2YHUYLHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 &LUFXLW 'HVFULSWLRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 (OHFWULFDO &KDUDFWHULVWLFV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Typical Supply Current ,DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3DFNDJH 2XWOLQHV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Plastic-Package, P-TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Plastic-Package, P-DSO-14-1(SMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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* Low operating current consumption (typically 3.5 mA) * High input sensitivity, high input frequencies (220 MHz) * Extremely fast phase detector without dead zone 3'62 * Linearization of the phase detector output by current sources 30% 5 * Synchronous programming of the counters (n-, n/a-, r-counters) and system parameters * Fast modulus switchover for 65-MHz operation * Switchable modulus trigger edge * Large dividing ratios for small channel spacing A scaler 0 to 127 376623 N scaler 3 to 16.380 R scaler 3 to 65.535 * Serial control (3-wire bus: data, clock, enable) for fast programming (Imax ~ 10 MHz) * Switchable polarity and phase detector current programmable * 2 Multifunction outputs * Digital phase detector output signals (e.g. for external charge pump) * Irn, Ivn outputs of the R and N scalers * Port 1 output (e.g. for standby of the prescaler) * External current setting for PD output * Lock detect output with gated anti-backlash pulse (quasi digital lock detect) 7\SH
PMB 2306T PMB 2306T PMB 2306R
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Q67100-H6423 Q67106-H6423 Q-67106-H6514 (T&R)
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P-DSO-14 (SMD) P-DSO-14 (SMD, Tape & Reel) P-TSSOP-16 (SMD, T&R)
The PMB 2306T PLL is a high speed CMOS IC, especially designed for use in battery powered radio equipment and mobile telephones. The primary applications will be in digital systems e.g. GSM, PCN, ADC, JDC and DECT systems. The wide range of dividing ratios also allows application in modern analog systems Semiconductor Group 4 02.97
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LD MFO2 MFO1 VDD1 PD VSS1 FI NC
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Positive supply voltage for serial control logic. Ground for serial control logic. Positive supply voltage for the preamplifiers, counters, phase detector and charge pump. Ground for the preamplifiers, counters, phase detector and charge pump. (1RWH 7KH SLQV 9'' DQG 9'' UHVSHFWLYHO\ 966 DQG 966 KDYH WR KDYH WKH VDPH VXSSO\ YROWDJH.) /LQH %XV (QDEOH Enable line of the serial control with internal pull-up resistor. When EN = H the input signals CLK and DA are disabled internally. When EN = L the serial control is activated. The received data are transferred into the latches with the positive edge of the EN-signal. /LQH %XV 'DWD Serial data input with internal pull-up resistor. The last two bits before the EN-signal define the destination address. In a byteoriented data structure the transmitted data have to end with the EN-signal, i.e. bits to be filled in (don't care) are transmitted first. /LQH %XV &ORFN Clock line with internal pull-up resistor. The serial data are read into the internal shift register with the positive edge (see pulse diagram for serial data control). 0RGXOXV &RQWURO 2XWSXW for external dual modulus prescaler. The modulus output is low at the beginning of the cycle. When the a-counter has reached its set value, MOD switches to high. When the n-counter has reached its set value, MOD switches to low again, and the cycle starts from the top. When the prescaler has the counter factor P or P + 1 (P for MOD = H, P + 1 for MOD = L), the overall scaling factor is NP + A. The value of the acounter must be smaller than that of the n-counter. The trigger edge of the modulus signal to the input signal can be selected (see programming tables and MOD A, B) according to the needs of the prescaler. In single modulus operation and for standby operation in dual modulus operation, the output is low.
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FI 9&2)UHTXHQF\ Input with highly sensitive preamplifier for 14-bit n-counter and 7-bit a-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. 5HIHUHQFH )UHTXHQF\ Input with highly sensitive preamplifier for 16-bit r-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. 3KDVH 'HWHFWRU Tristate charge pump output. The integrated, positive and negative current sources can be programmed with respect to their current density by means of the serial control. Activation and deactivation depend on the phase relationship of the scaled-down input signals FI:N, RI:R. (See phase detector output waveforms.) frequency IV < IR or IV lagging: p-channel current source active frequency IV > IR or IR leading: n-channel current source active frequency IV = IR and PLL locked: current sources are switched off, PD-output is tristate In standby mode the PD-output is set to tristate. The assignment of the current sources to the output signals of the phase detector can be swapped in it's polarity, i.e. the sign of the phase detector constant can be controlled. /RFN 'HWHFWRU 2XWSXW (open drain). Unipolar output of the phase detector in the form of a pulse-width modulated signal. The L-pulse width corresponds to the phase difference. Phase differences < 20 ns are not indicated due to gating of the antibacklash impuls. In the locked state the LD-signal is at H-level. In standby mode the output is resistive. Only for ABL status 11 no gating of ABL impulse is performed.
1
1
RI
10
12
PD
14
16
LD
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MFO1 MFO2 0XOWLIXQFWLRQ 2XWSXW for the signals IRN, V, VN and port 1. 0XOWLIXQFWLRQ ,23LQ for the output signals IVN, RN and the input signal ,REF. - The signals R and V are the digital output signals of the phase and frequency detector for use in external active current sources (see phase detector output wave forms). - The signals IRN and IVN are the scaled down signals of the reference frequency and VCO-frequency. The L-time corresponds to 1/IRI and 1/IFI respectively. - In the port function the port 1 output signal is assigned to the information of the status program. The output switches with the rising edge of the EN-signal. The standby mode does not affect the port function. - In the internal charge pump mode the input signal ,REF determines the value of the PD-output current. Reference current for charge pump:
,REF = (9DD - 9REF)/R1
= 100A (tolerance of 20% or less is recommended)
R1:see application circuit 9REF:see AC/DC characteristics
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*HQHUDO 'HVFULSWLRQ The circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a phase detector with charge pump output and a serial control logic. The setting of the operating mode and the selection of the counter ratios is done serially at the ports CLK, DA and EN. The operating modes allow the selection of single or dual operation, asynchronous or synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PDoutput current modes, polarity setting of the PD-output signal, adjustment of the triggeredge of the MOD-output signal, 2 standby modes and the control of the multifunction outputs MFO1 and MFO2. The reference frequency is applied at the RI-input and scaled down by the r-counter. It's maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and scaled down by the n- or n/a-counter according to single or dual mode operation. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode operation. The phase and frequency sensitive phase detector produces an output signal with adjustable anti-backlash impulses in order to prevent a dead zone for very small phase deviations. Phase differences of less than 100 ps can be resolved. In general the shortest anti-backlash pulse gives the best system performance. 3URJUDPPLQJ Programming of the IC is done by a serial data control. The contents of the message are assigned to the functional units according to the address. 6LQJOH RU GXDO PRGH RSHUDWLRQ DV ZHOO DV DV\QFKURQRXV RU V\QFKURQRXV GDWD DFTXLVLWLRQ LV VHW E\ VWDWXV DQG VKRXOG WKHUHIRUH SUHFHGH WKH SURJUDPPLQJ RI WKH FRXQWHUV 'DWD DFTXLVLWLRQ The PMB 2306T offers the possibility of synchronous data acquisition to avoid error signals at the phase detector due to non-corresponding dividing factors in the counters produced by asynchronous loading. Synchronous programming guarantees control during changes of frequency or channel. That means that the state of the phase detector or the phase difference is kept maintained, and in case of "lock in", the control process starts with the phase difference "zero".
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This is done as follows: 1.Setting of synchronous data acquisition by status 2. 2.Programming of the r-counter, status 1 (optional)-data is being loaded into shadow registers. 3.Programming of the n- or n/a-counter-data is being loaded into shadow registers, the EN-signal starts the synchronous loading procedure. 4.Synchronous programming - which means data transfer of all data from the shadow registers to the data registers - takes place at that point in time when the respective counter reaches "zero + 1", the maximum repetition rate for channel change is therefore IFI:N. 5.Transfer of status 1 information into the corresponding data register is tied to the ncounter loading, but follows the loading of the n-data register in the distance of one ncounter dividing ratio, this guarantees that for example a new PD-current value becomes valid at the same time when the counters are loaded with the new data. Synchronous avoids additional phase error caused by programming. Synchronous data acquisition is of especial advantage, when large steps in frequency are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid - "rough" - transient response. This method increases the fundamental frequency nearly by the square route of the reference frequency relation. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A "fine" lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN, DECT, DAMPS, JDC, PHP systems the synchronous mode should be used to get best performance of the PMB 2306T. 6WDQGE\ &RQGLWLRQ The PMB 2306T has two standby modes (standby 1, 2) to reduce the current consumption. Standby 1 switches off the whole circuit, the current consumption is reduced below 1 A. Standby 2 switches off the counters, the charge pump and the outputs, only the preamplifiers stay active. The standby modes do not affect the port output signal. For the influence on the other output signals VHH VWDQGE\ WDEOH 1RWH I51 I91 51 DQG 91 DUH WKH LQYHUWHG VLJQDOV RI I5 I9 5 DQG 9
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* In general the shortest anti-backlash pulse gives the best system performance. ** No ABL (Anti-Backlash-Pulse) gating performed. This means, that at the LD output the anti-backlash pulse will appear. In the other cases the anti-backlash pulse will be surpressed at the LD output.
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FI-input frequency, single HF-mode FI-input frequency, single LF-mode FI-input frequency, dual mode, FI-trigger edge LH, MOD A FI-input frequency, dual mode, FI-trigger edge HL, MOD B
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2XWSXW 3LQV 6WDWXV Standby 1 Standby 2 0)2 9 low low 91 high high high high resistive resistive tristate tristate low low 0)2 /' 3' 02'
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6WDWXV 6WDWXV 0 Data acquisition mode Mode 1 Mode 2 PD-polarity Standby 1 Standby 2 Anti-backlash pulse width 1 Anti-backlash pulse width 2 Preamplifier select Single / dual mode 1 2 3 4 5 6 EN Port 1 PD-current 1 PD-current 2 PD-current 3 0 0 Address 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EN single low see table see table see table asynchronous synchronous see table see table negative standby standby see table see table see table dual high positive active active 1
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'XDO 0RGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 EN 1 0 Address LSB LSB 1 0 n-Counter LSB MSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EN a-Counter MSB 6LQJOH 0RGH
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Supply voltage Input voltage Output voltage Power dissipation per output Total power dissipation Ambient temperature Storage temperature
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- 0.3 - 0.3 GND
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Supply voltage Input frequency dual mode Input frequency single HF-mode Input frequency single LF-mode Input reference frequency Input frequency dual mode Input frequency single HF-mode Input frequency single LF-mode Input reference frequency PD-output current PD-output voltage PD-output voltage Ambient temperature
9DD IFI IFI IFI IRI IFI IFI IFI IRI
/ ,PD / 9PD 9PD
3.0 0.1 0.1 0.1 0.1 0.1 0.1
5.5 65 220 90 100 30 120 35 22 4
V MHz MHz MHz MHz MHz MHz MHz MHz mA V V C
9DD = 4.5 ... 5.5 V 9DD = 4.5 ... 5.5 V 9DD = 4.5 ... 5.5 V 9DD = 4.5 ... 5.5 V 9DD = 3.3 V 9DD = 3.3 V 9DD = 3.3 V 9DD = 3.3 V 9DD = 4.5 - 5.5 V 9DD = 3.3 V
0.5 0.5 - 40
9DD - 0.5 9DD - 0.5
85
7A
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either 9DD or 9SS.
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9DD ,DD ,DD ,DD ,DD
3.3 1.63 1.76 0.11 5 2.6 2.80 0.62 5.5 2.94 3.17 0.75 1 V mA mA mA A Test conditions: IFI = 50 MHz, 9FI = 150 mVrms IRI = 10 MHz, 9RI = 150 mVrms ,PD = 0.25 mA, ,ref = 100 A
Supply voltage Supply current singlemode HF dual mode standby 2 standby 1
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0.7 9DD 0
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9I = 9DD = 5.5 V 9I = GND
Further information about timing see at page 25 and 26 ,QSXW 6LJQDO 5,
Input voltage Input voltage Slew rate Input capacity H-input current L-input current
9I 9I &I ,H ,L
100 100 2.5 3 30 - 30
mVrms I = 4 ... 100 MHz, 9DD =4.5 V mVrms I = 4 ... 22 MHz, 9DD = 3.3 V 9DD = 3.3 ... 5.5 V V/s pF A 9I = 9DD = 5.5 V A 9I = GND
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Input voltage Input voltage Input voltage Slew rate Input capacity H-input current L-input current
9I 9I 9I &I ,H ,L
180 180 50 4 3 30 - 30
mVrms mVrms mVrms V/s pF A A
I = 4 ... 65 MHz, 9DD = 4.5 V I = 4 ... 30 MHz, 9DD = 3.3 V I = 10 ... 30 MHz, 9DD = 3.3 V 9DD = 3.3 ... 5.5 V 9I = 9DD = 5.5 V 9I = GND
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Input voltage Input voltage Input voltage Slew rate Input capacity H-input current L-input current
9I 9I 9I &I ,H ,L
200 20 50 2.5 3 30 - 30
mVrms mVrms mVrms V/s pF A A
I = 4 ... 220 MHz, 9DD = 4.5 V I = 4 ... 120 MHz, 9DD = 3.3 V I = 10 ... 50 MHz, 9DD = 4.5 V 9DD = 3.3 ... 5.5 V 9I = 9DD = 5.5 V 9I = GND
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Current mode "0.175 mA" "0.25 mA" "0.35 mA" "0.5 mA" "0.7 mA" "1.0 mA" "1.4 mA" "2.0 mA" "Standby" * guaranteed by design
,PROG ,PROG ,PROG ,PROG ,PROG ,PROG ,PROG ,PROG / ,PD /
- 20 % - 20 % - 20 % - 20 % - 20 % - 10 % - 10 % - 10 % 0.1*
+ 20 % + 20 % + 20 % + 20 % + 20 % + 10 % + 10 % + 10 % 50
mA mA mA mA mA mA mA mA nA
9DD = 4.5 ... 5.5 V 9PD = 9DD/2 ,REF = 100 A
9DD = 5.5 V
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,PD / ,PROG ,PD / ,PROG - 20 % 4% +3%
9PD = 9DD/2, 9DD = 3.3 V 9PD = 1 ... 4 V, 9DD = 5 V
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Reference voltage
9REF
0.9
1.1
1.3
V
9DD = 4.5 ... 5.5 V, ,REF = 100 A
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V V V V ns ns ns ns
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9DD = 4.5 ... 5.5 V, ,QH = 2 mA 9DD = 4.5 ... 5.5 V, ,QL = 2 mA 9DD = 3.3 V, ,QH = 1.2 mA 9DD = 3.3 V, ,QL = 1.2 mA 9DD = 4.5 ... 5.5 V, &I = 10 pF 9DD = 4.5 ... 5.5 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF
2XWSXW 6LJQDO 0)2 SXVK SXOO H-output voltage L-output voltage H-output voltage L-output voltage Rise time Fall time Rise time Fall time
9QH 9QL 9QH 9QL WR WF WR WF
9DD - 1 9DD - 1
2 2 3 3 1 1 10 10 10 10
V V V V ns ns ns ns
9DD = 4.5 ... 5.5 V, ,QH = 2 mA 9DD = 4.5 ... 5.5 V, ,QL = 2 mA 9DD = 3.3 V, ,QH = 1.2 mA 9DD = 3.3 V, ,QL = 1.2 mA 9DD = 4.5 ... 5.5 V, &I = 10 pF 9DD = 4.5 ... 5.5 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF
2XWSXW 6LJQDO /' QFKDQQHO RSHQ GUDLQ L-output voltage L-output voltage Fall time Fall time
9QL 9QL WF WF
3 4.5
0.4 0.4 10 10
V V ns ns
9DD = 4.5 ... 5.5 V, ,QL = 0.5 mA 9DD = 3.3 V, ,QL = 0.5 mA 9DD = 4.5 ... 5.5 V, &I = 10 pF 9DD = 3.3 V, &I = 10 pF
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/LVW RI &RPSRQHQWV ,WHP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 4XDQWLW\ 5HIHUHQFH 1 2 1 1 1 1 4 1 1 1 3DUW 100 150 220 330 3.3 k 6.8 k 8.2 k 18 k 22 k 39 k 22 nH 1.2 pF 2.2 pF 10 pF 22 pF 33 pF 100 pF 330 pF 560 pF 5.6 nF 100 nF 22 F BBY 51 BFR 280 BFT 92 SMD/0805 B54102-A1101-K60 SMD/0805 B54102-A1151-J60 SMD/0805 B54102-A1221-J60 SMD/0805 B54102-A1331-J60 SMD/0805 B54102-A1332-J60 SMD/0805 B54102-A1682-J60 SMD/0805 B54102-A1822-J60 SMD/0805 B54102-A1183-J60 SMD/0805 B54102-A1223-J60 SMD/0805 B54102-A1393-J60 SIMID 01 B82412-A3220-M COG/0805 B37940-K5010-C262 COG/0805 B37940-K5020-C262 COG/0805 B37940-K5100-J62 COG/0805 B37940-K5220-J62 COG/0805 B37940-K5330-J62 COG/0805 B37940-K5101-J62 COG/0805 B37940-K5331-J62 COG/0805 B37940-K5561-J62 COG/1210 B37949-K5562-J62 X7R/1210 B37950-K5104-K62 B45196-E3226-+409 Q62702-B631 Q62702-F1298 Q62702-F1062 S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M S+M SIEMENS SIEMENS SIEMENS S+M S+M SIEMENS SIEMENS SIEMENS SIEMENS
57 513, 514 56 58 510 512 59, 53, 55, 511 54 52 52
1 /1 1 1 1 6 3 1 1 1 1 1 1
&11 &13 &8 &20, &10, &12, &14, &15, &16 &17, &1, &2 &9 &3 &5 &7 &6 &19
1 D1 2 T3, T2 1 T1 1 2 1 1 &4 X2, X1 RX IC1
1 IC2
1,0 nF COG/1210 B37949-K5102-J62 SMA Connector 1.3 GHz B69610-G1307-A412 PMB 2306T P-DSO-14 Q67100-H6423 PMB 2306T P-DSO-14 Q67106-H6423(T+R) PMB 2314 P-DSO-8 Q67000-A6121 PMB 2314 P-DSO-8 Q67006-A6121(T+R)
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6RUWV RI 3DFNLQJ Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 35
Dimensions in mm 02.97
GPM05247

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